The Advanced Thin Film Process & Technology is a session to focus on the latest research results related to thin film materials, processing, and device manufacturing for the emerging memory and logic semiconductor applications. In response to ever-growing semiconductor market advancing toward higher density and better performance, advanced thin film processing with atomic scale fidelity which can enable alternative materials and complex 3D device structure is becoming increasingly more important for the extremely scaled semiconductor integration. Therefore, the main purpose of this session is to introduce the latest research results on advanced thin film technologies, surface science, and inorganic/organic chemistry for newly required materials and their device applications. In addition, theoretical simulation of thin film deposition reactions and development of chemical precursors will be introduced in this session. This symposium brings together a broad community of researchers from a variety of fields including materials science, surface science, inorganic chemistry, condensed matter physics, electrical engineering, and quantum information science to exchange the latest research results and to create a new frontier for thin film deposition-related researchers.

• Thin films to semiconductor applications
• Chemical and physical based deposition for semiconductors
• Atomic layer deposition and its semiconductor applications
• Area selective deposition method for future semiconductors
• Precursor development for CVD and ALD
• Thin film reaction simulation
• Topics related with semiconductor thin films

The CMP& Post CMP Cleaning session will focus and discuss the research on novel functional CMP process, CMP slurry, and post cleaning for scaling-down logic and memory devices, being able to perform fast polishing rate, high polishing rate, high polishing rate selectivity, dishing-free, erosion-less, scratch-less, and remaining particle-less for inorganic, organic, and metal film CMPs. In addition, several CMP mechanisms will be reviewed by the applied surface science such as dynamic mechanical and chemical behavior. Beyond conventional CMP abrasives such as colloidal silica and zirconia etc., novel CMP abrasives such as core/shell abrasives and chemical deliverable abrasives will be introduced. Moreover, new indispensable CMP processes will be discussed as the memories and logic devices has scaled down and the following CMP slurry and post-cleaning will be debated. Furthermore, as the design rule of DRAM, 3D NAND flash memory, logic device has scaled down less than 10 nm, 256 floors, and 2 nm, the presence of a physical limit or not will be discussed for a CMP application.

• CMP process, CMP slurry, post-cleaning process for STI, ILD, poly silicon, nitride, tungsten, copper, amorphous carbon, and GeSbTe film planarization.
• Super-fine(abrasive dimeter: < 5 nm) ceria CMP slurry, related post cleaning, and CMP process application.
• Extremely high surface topography(i.e., > 1 μm) CMP slurry and process.
• Self-stop CMP slurry and process.
• Amorphous carbon and spin-on-glass CMP slurry and process.
• Core/shell(inorganic/organic & organic/organic) abrasive based CMP slurry and CMP performance.
• Chemical deliverable abrasive based CMP slurry and CMP performance.
• Eco-friendly post cleaning chemical and process.
• Structure induced stress simulation and stress induced CMP defects.

As the device integration is increased continuously, the critical dimension of semiconductor device has decreased to a few nanometers and the device structure is changing from two dimensional (2D) structures to three dimensional (3D) structures. Due to the complexity of the device fabrication and the use of various materials for the semiconductor devices, the etching technology has become one of the most difficult technologies for next generation semiconductor device fabrication requiring low damage etching, highly selective etching, high aspect ratio etching, etc. on 2D and 3D structured materials. In this session, the advanced etch technologies such as ALE, cyclic etching, pulsed plasma etching, etching with low GWP materials, etc. which are required for the next generation semiconductor device fabrication will be presented. The researchers and engineers working in the etching of the semiconductor and display materials are welcome to this session, and encouraged to attend and present their works in this session.

• New Etching process
• Etching mechanism
• Plasma diagnostics & monitoring
• Plasma sources for etching

The field of lithography faces a challenging task of extending into ever-shrinking generations while remaining cost-effective and manufactural. State-of-the-art processes such as immersion lithography and multiple patterning have been implemented to address this challenge, with EUV lithography making significant progress and starting to be employed for mass production. Moreover, a high-NA EUV tool is expected to be delivered soon, which is poised to further enhance the capabilities of EUV lithography. To complement these efforts, the lithography community is actively pursuing alternative patterning approaches and complementary solutions. Success in this field necessitates unique interdisciplinary interactions and coordinated efforts between lithographers, layout designers, materials scientists, and metrology/process control engineers to enable cost-efficient patterning solutions. This symposium covers a broad spectrum of lithography and patterning topics, attracting participants from diverse backgrounds to share and learn about state-of-the-art lithographic tools, resists, metrology, materials, design, process integration, and novel approaches. The symposium also fosters provocative discussions and seminars to address current issues in the field, such as extending current methods, exploring alternative approaches, and identifying new ways to complement existing technologies.

• EUV Lithography : EUV scanner, EUV tool, EUV mask, EUV OPC, EUV Patterning material
• Patterning Materials: EUV resist, photoresists for optical lithography, materials for alternative lithography, photopatternable functional materials
• Nano Fabrication for next generation optical devices: Nanoprinting for optical metasurfaces, printable nanolasers
• Alternative Lithography: 3D Patterning, Imprinting, Self-assemble, non-conventional lithography
• Layout optimization & Computational Lithography: DTCO(design technology co-optimization), DFM(design for manufacturing), SMO(source mask optimization)
• Advanced Metrology and Inspection: optical inspection, interference microscopy, advanced process control, overlay metrology, computational metrology
• Applications and Related Emerging Topics

As the demand for low-power, multi-functional semiconductors continues to grow, the industry faces a challenge to find alternative materials, processes, devices, and systems to meet these demands. One approach to addressing these challenges is through advanced packaging technology, which has become another driving force for semiconductor technology development. Advanced packaging technology involves creating packages or housings for integrated circuits that go beyond traditional chip-scale packaging and includes technologies such as fan-out wafer-level packaging (FO-WLP), 3D packaging, and heterogeneous integration.
 
Heterogeneous integration, which includes 3D IC, system-in-package, and monolithic 3D (M3D), has garnered much interest in the industry due to its potential to improve device performance, increase functionality, and reduce form factor. In this regard, the heterogeneous integration packaging will focus on advanced packaging materials, processes, and integrations for a range of applications such as mobile, high-performance computing (HPC), automotive, 5G, health, and chiplets.
 
The session will cover a wide range of topics related to heterogeneous integration, including the latest developments in advanced packaging materials such as underfill, die attach, and encapsulants; new packaging processes such as through-silicon vias (TSVs), wafer-level bonding, and fan-out panel-level packaging (FO-PLP); and innovative integration approaches such as system-in-package (SiP) and monolithic 3D (M3D). Through these discussions, we aim to promote knowledge sharing, identify key challenges, and explore solutions that will drive the next generation of advanced packaging technology for the semiconductor industry.

• Advanced packaging for heterogeneous integration
• 2.5D and 3D packaging technology
• Fan-out and Fan-In technology
• Hybrid and direct bonding for 3D integration
• Thermal/mechanical simulation & characterization
• Advanced device and system using heterogeneous integration
• Monolithic 3D integration
• Topics related with heterogeneous integration

The advancement in IC manufacturing has introduced novel fabrication techniques such as three-dimensional stacked integrated circuit (3DS-IC) fabrication and emerging devices including PIM, ferroelectrics, and new types of transistors. However, these new techniques have presented challenges for both in-line and ex-situ metrology and characterization.
The production of 3DS-ICs requires complex processes such as high-aspect ratio through-silicon vias (TSVs), thin wafer handling and processing, wafer thinning, and bonding of thin wafers with complex patterned surfaces, each of which pose unique metrology challenges. Additionally, 3D gate stack integration creates atomic scale defect control issues that were not previously encountered in planar FETs.

Moreover, emerging devices like ferroelectric FETs, TFETs, and NCFETs, developed for PIM and steep switching MOSFETs, demand frontier metrology for ultrathin materials and interfaces. Effective process monitoring metrology and nano-scale particles and contamination control are also critical to achieve high device-to-device and lot-to-lot uniformity and target device properties.

Therefore, the purpose of this symposium is to introduce the latest research results on various nano-scale analysis and process modeling on thin films, interfaces, particles, defects, and contaminations in advanced IC manufacturing including but not limited to 3D device integration and emerging devices and materials as well as process diagnosis and monitoring metrology.

• Topics related with physical and chemical analysis of 3D device integration
• Topics related with physical and chemical analysis of nano-scale particles and defects
• Topics related with chemical analysis of contaminations on organic and inorganic materials
• Topics related with MI in the emerging semiconductor process
• Topics related with diagnosis for control semiconductor process

High-performance power transistors are essential for high efficient power conversion in the future mobility systems such as electric vehicle, flying car, fuel cell transportation. This Power TR session will focus and discuss the research from material growth to device, package, and driving circuit, system employing the advanced power transistors (MOSFET, IGBT, BJT, MESFET, HEMT, HBT). TCAD-based design for novel Si technologies (super junction MOSFET and trench-stop IGBT), III-V compound semiconductor based high-frequency GaN power transistor and IV-IV compound semiconductor based high-power SiC and Diamond transistor will be introduced. In addition, advanced fabrication process and packaging technologies for power transistor as well as design of gate-driving circuit to improve power switching performance will be reviewed in this session. Moreover, testing technologies for power transistor are getting important to improve their short-term and long-term reliability even under harsh environment with high-temperature or radiation to be applied for aerospace and drone applications.

• Material growth (Substrate, Epitaxial growth of SiC, GaN, Diamond)
• Fabrication process (Implantation, oxidation/deposition for interface, etching, metal, diffusion, wafer thinning)
• TCAD simulation and layout technologies (Si MOSFET, Si IGBT, GaN HEMT, SiC MOSFET, Diamond JFET, etc.)
• Characterization of device or process for power transistors (static, dynamic, X-ray, thermal, etc.)
• Short-term (UIS, short-circuit, breakdown, SEE) and long-term (HTGB/HTRB, TCT, PCT, TID) reliability
• Design of analog/digital circuit using power transistor and gate driving circuit
• Novel power conversion or management system using power transistor
• Chip and module packaging technology

The Electronic Materials, Devices and Related technology session will focus and open discuss on other topics not include session 01 - session 07 but all electronic materials, devices and software, and semiconductor related topics. This session included the same scopes to the fall conference of KSDT 2023, therefor there is no limitations. After reviewing process, the program committee will allocate their research results to the most close topic session.

• Design of future nanoscale semiconductor devices
• Synthesis of nanomaterials and characterizations for applications
• Oxide and nitride based semiconductors and their applications
• Fundamentals and applications of Display technology
• Optoelectronics and various sensors
• Power devices and applications
• Semiconductor circuits design related topics
• Development of PIM related topics
• Application of novel materials for future electronic devices
• AI related hardware and software
• Topics related with semiconducting physics and technology